From EP 0 422 776 is known a communication system for serial data exchange which comprises a microprocessor, a memory, a DMA unit (Direct Memory Access Control unit DMAC) and a serial interface (Serial Communication Control SCC). These function blocks are interconnected by a data bus as shown in FIG. 3 (column 4, lines 6-26). In FIG. 3 with respective description (column 8, line 41 to column 9, line 12) a description is given of how the data (communication line 318) is received by the interface (SCC). Subsequently, under the control of the DMAC, the address information and the message contents of the data packets are written in a specified memory location in the memory via the data bus (310). In this phase, the interface (SCC) does not apply any control signals to the microprocessor. The DMA unit (DMAC) controls the transmission of the data packets from the interface (SCC) to the memory without controlling the operation and thus a possibility of reacting to deviations from the normal operation (column 8, lines 41-47).
This means that the data exchange always takes place in the DMA mode in which the DMA unit controls the transfer to the memory. Since the defined communication system does not have a control line from the interface to the microprocessor, the serial interface cannot be used in the conventional interrupt mode. In an interrupt mode the interface informs the microprocessor by way of a control signal (interrupt) of any change of mode (for example, ready to receive, data received, data sent, addressing/initialization of a transmission on the bus, and so on) during the data exchange. This conventional kind of control of the data exchange, however, causes a considerable load on the microprocessor and on the data bus which can consequently render considerably less capacity available for other purposes (for example, the control of further interfaces). More particularly with high clock rates on the data bus (for example, 400 kbit IIC bus) or large data sequences to be transmitted (for example, for a graphics display) the microprocessor is nearly exclusively busy with processing the interrupt requests of the interface.